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Nolan’s Notes: Coming to Terms With AIiNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
April 26, 2024 | iNEMIEstimated reading time: 1 minute
Advanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit. With a unified platform, chip designers creating hyperscale computing, consumer, 5G communications, mobile and automotive applications can achieve greater productivity versus a disjointed die-by-die implementation approach.
Cadence is one of the first to provide EDA solutions for advanced packaging and heterogeneous integration and is leading the industry in delivering them to market for better design with greater efficiency. This presentation will review advanced packaging technology trends and provide an overview of Cadence’s EDA platforms that enable seamless design from front-end to back-end for the new era of advanced semiconductor packaging.
About Sang-Hyun Lee, Ph.D.
Sr. Principal Product Engineer
Custom IC, Packaging and PCB Development Group
Cadence Design Systems / Seoul, Korea
Sang-Hyun Lee joined Cadence in 2023 and is working in development of Cadence EDA tools for advanced semiconductor packages. Prior to joining Cadence, he worked at Amkor Technology and Samsung Electronics in semiconductor package development. He had led multiple projects developing advanced packages such as 2.5D packages, wafer-level fan-out packages, MCM FCBGAs, CPO (Co-Packaged Optics) and SiPs.
Dr. Lee received his Ph.D. in Electrical Engineering from the University of Michigan (Ann Arbor, Michigan, USA). He has a master’s degree in material science from Korea Advanced Institute of Science and Technology (KAIST) (Daejon, Korea) and a bachelor’s degree in metallurgical engineering from Korea University (Seoul, Korea).
Registration
This webinar is open to industry; advance registration is required (see link below). If you have any questions or need additional information, please contact Masahiro Tsuriya.
Tuesday, May 21, 2024
10:00-11:00 a.m. JST (Japan)
9:00-10:00 p.m. EDT on Monday May 20 (US)
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iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
05/13/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling.
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